Chronos
Chronos is a chip that I designed in TSMC 65nm CMOS during my master thesis and finally sent it for tape-out at July 2020. The transmitter is based on a digital intensive PLL at 2.4GHz which includes a new type of TDC based on a differential current ramp and a SAR ADC. The digital logic includes all the logic for the PLL, SPI and also GFSK modulation data generation at 1Mbps and 2Mbps datarates. In the chip are integrated also two RF PAs, one based on first-order sigma-delta based DC/DC converter with a bootstrap switch and the other one is a Class-D PA. The bandgap reference (BGR) and the SAR ADC are designed by other designers in the group. The main target in this design is low power and all the blocks are designed with this goal while complying with the specification of the BLE protocol. The PLL is based on a Class-C DCO with enough tuning range to compensate for the process variations and two feedback loops to ensure the correct start-up and voltage setup.
Chronos is a chip that I designed in TSMC 65nm CMOS during my master thesis and finally sent it for tape-out at July 2020. The transmitter is based on a digital intensive PLL at 2.4GHz which includes a new type of TDC based on a differential current ramp and a SAR ADC. The digital logic includes all the logic for the PLL, SPI and also GFSK modulation data generation at 1Mbps and 2Mbps datarates. In the chip are integrated also two RF PAs, one based on first-order sigma-delta based DC/DC converter with a bootstrap switch and the other one is a Class-D PA. The bandgap reference (BGR) and the SAR ADC are designed by other designers in the group. The main target in this design is low power and all the blocks are designed with this goal while complying with the specification of the BLE protocol. The PLL is based on a Class-C DCO with enough tuning range to compensate for the process variations and two feedback loops to ensure the correct start-up and voltage setup.
Chronos is a chip that I designed in TSMC 65nm CMOS during my master thesis and finally sent it for tape-out at July 2020. The transmitter is based on a digital intensive PLL at 2.4GHz which includes a new type of TDC based on a differential current ramp and a SAR ADC. The digital logic includes all the logic for the PLL, SPI and also GFSK modulation data generation at 1Mbps and 2Mbps datarates. In the chip are integrated also two RF PAs, one based on first-order sigma-delta based DC/DC converter with a bootstrap switch and the other one is a Class-D PA. The bandgap reference (BGR) and the SAR ADC are designed by other designers in the group. The main target in this design is low power and all the blocks are designed with this goal while complying with the specification of the BLE protocol. The PLL is based on a Class-C DCO with enough tuning range to compensate for the process variations and two feedback loops to ensure the correct start-up and voltage setup.
